1. Field of the Invention
The invention relates to a circuit arrangement for converting an analogue signal expressed as a magnitude of an electric voltage U.sub.A into a digital signal and/or for converting a digital signal into an analogue signal, and further relates to a process for the operation of the circuit arrangement.
2. Description of the Prior Art
In measuring and regulating technology, analogue-digital converters (which in the following will also be abbreviated as ADC), are frequently required to facilitate a data-wise detection of an analogue signal, and a further processing of the signal with digital calculating systems. In addition, digital-analogue converters are required to obtain from a digital value an analogue signal with which a system can be regulated, for example. Such analogue-digital and digital-analogue converters should exhibit as high as possible a resolution such that the time required for the conversion may be as short as possible. Also the circuit arrangement for the converter should be capable of being constructed on a small area and on one single semiconductor chip.
In accordance with the prior art, various circuit arrangements are known for converting an analogue signal into a digital signal and vice versa. Thus, for example, the 1972 edition of "IEEE International Solid-State Circuits Conference," p. 146, describes a circuit arrangement with which an analogue signal can be converted into a digital signal in a very short length of time. The process on which this circuit arrangement is based consists in dividing a reference voltage for a N-bit converter into N-sub-voltages with the aid of a voltage divider and, with the aid of (2.sup.N -1) comparators, developing a decision as to which of these sub-voltages exceeds the input signal. A circuit arrangement suitable for this purpose thus requires, for example, for a 4-bit converter, 15 comparators, so that such circuit arrangements have a large space requirement and thus cannot be constructed on a small area on one semiconductor chip.
Another possibility of converting an analogue signal into a digital signal consists in altering the charge state of a capacitor with the analogue signal in the form of the value of an electric voltage U.sub.A and then, by a stepped recharging of this capacitor, determining the change in this charge state caused by the connection of the analogue signal. This can be effected on the one hand in that the analogue signal charges a capacitor, the capacitor is discharged in stepped fashion, and the number of individual discharge steps is counted, the digital signal corresponding to the analogue signal being formed by the number of counted discharge steps. Vice versa, it is also possible to partially discharge an already charged capacitor with the analogue signal U.sub.A, and, in individual recharging steps either to return the capacitor to the earlier state or to entirely discharge it, and to count the individual recharging steps. Circuit arrangements of this type can, with slight circuitry modifications, also be operated as digital-analogue converters. For this purpose a fixed quantity of charge is transported into a capacitance (capacitor) with a frequency in accordance with the digital number. In this case the voltage appearing across this capacitance changes by a specific amount with each charging step so that the voltage appearing across this capacitance after the end of the recharging steps corresponds to the digital number.
An example of a circuit arrangement with which it is possible to carry out such a process for converting an analogue signal into a digital signal is described in "IEEE international Solid-State Circuits Conference" 1974, p. 194 et seq. The fundamental circuit diagram of this arrangement is illustrated in FIG. 1. It consists of a capacitor C.sub.1 to which the analogue signal U.sub.A is connected via a first switch which, for example, can be a transistor T.sub.1, whereby the capacitor C.sub.1 becomes charged. When the transistor T.sub.1 has opened, the capacitor C.sub.1 is discharged in stepped fashion via a second switch which, for example, can be a transistor T.sub.4. This is effected in that when the transistor T.sub.4 is switched on, a portion of the charge of capacitor C.sub.1 is fed into a second capacitor C.sub.2 which has a substantially lower capacitance than the capacitor C.sub.1. Due to the fact that charge flows from the capacitor C.sub.1 to the initially uncharged capacitor C.sub.2, the voltage across the capacitor C.sub.2 increases. This rise in voltage is established by an evaluator circuit. The evaluator can, for example, be in the form of a transistor T.sub.3 which is switched into the conductive state whenever the voltage occurring across the capacitor C.sub.2 is greater than the start voltage of this transistor. When the capacitor C.sub.2 has been charged, and an evaluator pulse has been emitted, the capacitor C.sub.2 is brought back to the reference potential U.sub.Ref via a third switch, for example a transistor T.sub.2. When the switch T.sub.2 has opened, a new discharge step commences for the capacitor C.sub.1 as a result of the opening of the switch T.sub.4. These discharge steps are continued until the voltage occurring across the second capacitor C.sub.2 following the recharging is no longer sufficient to actuate the transistor T.sub.3 serving as an evaluator. The number of discharge steps required for this purpose is determined and is converted into the digital word. A circuit arrangement with which this process can be executed is shown in FIG. 1. This circuit arrangement, which is known from the prior art, is suitable for construction in integrated fashion with a small space requirement on one semiconductor chip. However, the operating process for this circuit arrangement has considerable disadvantages. These result on the one hand from the fact that in the stepped recharging from the capacitor C.sub.1 to the capacitor C.sub.2, a constant, fixed quantity of charge is not transported into the capacitor C.sub.2 on each occasion, but rather the quantity of charge transported into the capacitor C.sub.2 in an individual recharging step falls constantly with an increasing number of recharging steps. This is due to the fact that the quantity of charge flowing into the capacitor C.sub.2 is dependent upon the potential difference between the voltage in each case connected to the capacitor C.sub.1 and the reference voltage. This voltage difference reduces with increasing discharge of the capacitor C.sub.1. It is particularly disadvantageous that no linear relationship exists between the number of discharge steps and the value of the analogue signal U.sub.A. A further disadvantage consists in that the resolution of this circuit arrangement is dependent upon the ratio of the capacitances of the capacitor C.sub.1 and of the capacitor C.sub.2. For a very high resolution the capacitor C.sub.2 would have to be very much smaller than the capacitor C.sub.1 ; however, the value of capacitor C.sub.2 is governed by a lower limit since the capacitance of the capacitor C.sub.2 must be greater than the disruptive parasitic conductor path capacitances.
A further disadvantageous side effect consists in that further disruptive capacitances exist between the electrodes of the capacitor C.sub.1 and the gate electrode of the transistor T.sub.4 which serves as a switch; between the electrode of the capacitor C.sub.2 and the gate electrode of the transistor T.sub.4 ; and between the electrode of capacitor C.sub.2 and the gate electrode of the transistor T.sub.2 which switches the reference voltage. These parasitic capacitances cause a further inaccuracy in the conversion of the analogue signal into a digital signal since these disruptive capacitances must also be recharged during the recharging of the capacitor C.sub.1 or capacitor C.sub.2. The same difficulties occur when this arrangement is operated as a digital-analogue converter.